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Updated spirv-headers.

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This commit is contained in:
Бранимир Караџић
2026-06-14 09:25:50 -07:00
committed by Branimir Karadžić
parent 543a297f95
commit f44f23eb08
9 changed files with 330 additions and 43 deletions
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3rdparty/spirv-headers/include/spirv/spir-v.xml
Vendored
+6 -3
View File
@@ -82,7 +82,8 @@
<id value="47" vendor="ARM" comment="Contact Christopher Gautier, christopher.gautier@arm.com"/>
<id value="48" vendor="Goopax" comment="Contact Ingo Josopait, josopait@goopax.com"/>
<id value="49" vendor="Icyllis Milica" tool="Arc3D Shader Compiler" comment="Contact Icyllis Milica, https://github.com/BloCamLimb/Arc3D"/>
<unused start="50" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
<id value="50" vendor="Isochron" tool="Pred" comment="Contact Justin Ead, jebrim@isochrontechnologies.com"/>
<unused start="51" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
</ids>
<!-- SECTION: SPIR-V Opcodes and Enumerants -->
@@ -179,13 +180,14 @@
<ids type="enumerant" start="6784" end="6911" vendor="Intel" comment="Contact mariusz.merecki@intel.com"/>
<ids type="enumerant" start="6912" end="6975" vendor="Valve" comment="Contact michael.blumenkrantz@gmail.com"/>
<ids type="enumerant" start="6976" end="7039" vendor="Broadcom" comment="Contact gleese@broadcom.com"/>
<ids type="enumerant" start="7040" end="7103" vendor="Samsung" comment="Contact r.potter@samsung.com"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
<ids type="enumerant" start="7040" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<ids type="enumerant" start="7104" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
@@ -289,7 +291,8 @@
<!-- Reserved image operand bits -->
<ids type="ImageOperand" start="0" end="15" vendor="Khronos" comment="Reserved ImageOperand bits, not available to vendors - see the SPIR-V Specification"/>
<ids type="ImageOperand" start="16" end="16" vendor="Nvidia" comment="Contact pmistry@nvidia.com"/>
<ids type="ImageOperand" start="17" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="ImageOperand" start="17" end="17" vendor="Google" comment="Contact syoussefi@google.com"/>
<ids type="ImageOperand" start="18" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="ImageOperand" start="31" end="31" vendor="Khronos" comment="Reserved ImageOperand bit, not available to vendors"/>
</registry>
3rdparty/spirv-headers/include/spirv/unified1/ArmExperimentalMLOperations.h
Vendored
+26
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@@ -0,0 +1,26 @@
// SPDX-FileCopyrightText: 2025 Arm Ltd.
// SPDX-License-Identifier: MIT
#ifndef SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_
#define SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_
#ifdef __cplusplus
extern "C" {
#endif
enum {
ArmExperimentalMLOperationsRevision = 1,
ArmExperimentalMLOperationsRevision_BitWidthPadding = 0x7fffffff
};
enum ArmExperimentalMLOperationsInstructions {
ArmExperimentalMLOperationsCALL = 0,
ArmExperimentalMLOperationsInstructionsMax = 0x7fffffff
};
#ifdef __cplusplus
}
#endif
#endif // SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_
3rdparty/spirv-headers/include/spirv/unified1/NonSemanticGraphDebugInfo.h
Vendored
+28
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@@ -0,0 +1,28 @@
// SPDX-FileCopyrightText: 2022-2026 Arm Ltd.
// SPDX-License-Identifier: MIT
#ifndef SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_
#define SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_
#ifdef __cplusplus
extern "C" {
#endif
enum {
NonSemanticGraphDebugInfoRevision = 1,
NonSemanticGraphDebugInfoRevision_BitWidthPadding = 0x7fffffff
};
enum NonSemanticGraphDebugInfoInstructions {
NonSemanticGraphDebugInfoDebugGraph = 1,
NonSemanticGraphDebugInfoDebugOperation = 2,
NonSemanticGraphDebugInfoDebugTensor = 3,
NonSemanticGraphDebugInfoInstructionsMax = 0x7fffffff
};
#ifdef __cplusplus
}
#endif
#endif // SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_
3rdparty/spirv-headers/include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json
Vendored
+25
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@@ -0,0 +1,25 @@
{
"copyright": [
"SPDX-FileCopyrightText: 2025 Arm Ltd.",
"SPDX-License-Identifier: MIT"
],
"revision": 1,
"instructions": [
{
"opname": "CALL",
"opcode": 0,
"operands": [
{
"kind": "LiteralInteger",
"name": "Opcode"
},
{
"kind": "IdRef",
"quantifier": "*",
"name": "Parameters"
}
]
}
],
"operand_kinds": []
}
3rdparty/spirv-headers/include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json
Vendored
+35
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@@ -0,0 +1,35 @@
{
"copyright": [
"SPDX-FileCopyrightText: 2022-2026 Arm Ltd.",
"SPDX-License-Identifier: MIT"
],
"revision" : 1,
"instructions" : [
{
"opname" : "DebugGraph",
"opcode" : 1,
"operands" : [
{ "kind" : "IdRef", "name" : "Graph" },
{ "kind" : "IdRef", "name" : "Name" }
]
},
{
"opname" : "DebugOperation",
"opcode" : 2,
"operands" : [
{ "kind" : "IdRef", "name" : "DebugGraph" },
{ "kind" : "IdRef", "name" : "Name" },
{ "kind" : "IdRef", "name" : "Instructions", "quantifier" : "*" }
]
},
{
"opname" : "DebugTensor",
"opcode" : 3,
"operands" : [
{ "kind" : "IdRef", "name" : "Tensor" },
{ "kind" : "IdRef", "name" : "Name" },
{ "kind" : "IdRef", "name" : "Index", "quantifier" : "?" }
]
}
]
}
3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json
Vendored
+114 -20
View File
@@ -11,7 +11,7 @@
"magic_number" : "0x07230203",
"major_version" : 1,
"minor_version" : 6,
"revision" : 4,
"revision" : 7,
"instruction_printing_class" : [
{
"tag" : "@exclude"
@@ -5775,7 +5775,7 @@
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "LiteralString", "name" : "Data" }
{ "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Data" }
],
"capabilities" : [ "ConstantDataKHR" ],
"version" : "None"
@@ -5787,7 +5787,7 @@
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "LiteralString", "name" : "Data" }
{ "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Data" }
],
"capabilities" : [ "ConstantDataKHR" ],
"version" : "None"
@@ -6505,7 +6505,8 @@
{ "kind" : "IdRef", "name" : "Hit Object" },
{ "kind" : "IdRef", "name" : "Ray Query" },
{ "kind" : "IdRef", "name" : "SBT Record Index" },
{ "kind" : "IdRef", "name" : "Hit Object Attributes" }
{ "kind" : "IdRef", "name" : "Hit Object Attributes" },
{ "kind" : "IdRef", "quantifier" : "?", "name" : "Hit Kind" }
],
"capabilities" : [ "ShaderInvocationReorderEXT" ],
"version" : "None"
@@ -10802,8 +10803,8 @@
"aliases" : [ "OpReadPipeBlockingINTEL" ],
"opcode" : 5946,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pipe" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Packet Size" },
{ "kind" : "IdRef", "name" : "Packet Alignment" }
],
@@ -10816,8 +10817,8 @@
"aliases" : [ "OpWritePipeBlockingINTEL" ],
"opcode" : 5947,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pipe" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Packet Size" },
{ "kind" : "IdRef", "name" : "Packet Alignment" }
],
@@ -11222,8 +11223,6 @@
"class" : "Composite",
"opcode" : 6096,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "quantifier" : "*", "name" : "Constituents" }
],
"capabilities" : [ "LongCompositesINTEL" ],
@@ -11254,27 +11253,29 @@
"version" : "None"
},
{
"opname" : "OpControlBarrierArriveINTEL",
"opname" : "OpControlBarrierArriveEXT",
"class" : "Barrier",
"aliases" : [ "OpControlBarrierArriveINTEL" ],
"opcode" : 6142,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
"opname" : "OpControlBarrierWaitINTEL",
"opname" : "OpControlBarrierWaitEXT",
"class" : "Barrier",
"aliases" : [ "OpControlBarrierWaitINTEL" ],
"opcode" : 6143,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
@@ -11598,6 +11599,34 @@
"provisional" : true,
"version" : "None"
},
{
"opname" : "OpPredicatedLoadINTEL",
"class" : "Memory",
"opcode" : 6258,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Predicate" },
{ "kind" : "IdRef", "name" : "Default Value" },
{ "kind" : "MemoryAccess", "quantifier" : "?" }
],
"capabilities" : [ "PredicatedIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpPredicatedStoreINTEL",
"class" : "Memory",
"opcode" : 6259,
"operands" : [
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Object" },
{ "kind" : "IdRef", "name" : "Predicate" },
{ "kind" : "MemoryAccess", "quantifier" : "?" }
],
"capabilities" : [ "PredicatedIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
@@ -12522,9 +12551,10 @@
"version" : "None"
},
{
"enumerant" : "ForceOpacityMicromap2StateEXT",
"enumerant" : "ForceOpacityMicromap2StateKHR",
"aliases" : [ "ForceOpacityMicromap2StateEXT" ],
"value" : "0x0400",
"capabilities" : [ "RayTracingOpacityMicromapEXT" ],
"capabilities" : [ "RayTracingOpacityMicromapKHR" ],
"version" : "None"
}
]
@@ -12654,6 +12684,11 @@
"enumerant" : "Rust",
"value" : 13,
"version" : "1.0"
},
{
"enumerant" : "Pred",
"value" : 14,
"version" : "1.0"
}
]
},
@@ -13549,6 +13584,15 @@
"capabilities" : [ "FloatControls2" ],
"version" : "None"
},
{
"enumerant" : "OpacityMicromapIdKHR",
"value" : 6031,
"capabilities" : [ "RayTracingOpacityMicromapExecutionModeKHR" ],
"parameters" : [
{ "kind" : "IdRef", "name" : "Enable" }
],
"version" : "None"
},
{
"enumerant" : "StreamingInterfaceINTEL",
"value" : 6154,
@@ -14568,6 +14612,12 @@
"capabilities" : [ "Linkage" ],
"extensions" : [ "SPV_KHR_linkonce_odr" ],
"version" : "None"
},
{
"enumerant" : "WeakAMD",
"value" : 3,
"capabilities" : [ "WeakLinkageAMD" ],
"version" : "None"
}
]
},
@@ -17704,6 +17754,13 @@
"provisional" : true,
"version" : "None"
},
{
"enumerant" : "WeakLinkageAMD",
"value" : 5181,
"capabilities" : [ "Linkage" ],
"extensions" : [ "SPV_AMD_weak_linkage" ],
"version" : "None"
},
{
"enumerant" : "SampleMaskOverrideCoverageNV",
"value" : 5249,
@@ -18009,10 +18066,11 @@
"version" : "None"
},
{
"enumerant" : "RayTracingOpacityMicromapEXT",
"enumerant" : "RayTracingOpacityMicromapKHR",
"aliases" : ["RayTracingOpacityMicromapEXT"],
"value" : 5381,
"capabilities" : [ "Shader" ],
"extensions" : [ "SPV_EXT_opacity_micromap" ],
"extensions" : ["SPV_KHR_opacity_micromap", "SPV_EXT_opacity_micromap"],
"version" : "None"
},
{
@@ -18147,6 +18205,13 @@
"extensions" : [ "SPV_NV_tensor_addressing" ],
"version" : "None"
},
{
"enumerant" : "CooperativeMatrixDecodeVectorNV",
"value" : 5447,
"capabilities" : [ "CooperativeMatrixBlockLoadsNV" ],
"extensions" : [ "SPV_NV_cooperative_matrix_decode_vector" ],
"version" : "None"
},
{
"enumerant" : "SubgroupShuffleINTEL",
"value" : 5568,
@@ -18489,6 +18554,13 @@
"extensions" : [ "SPV_KHR_fma" ],
"version" : "None"
},
{
"enumerant" : "RayTracingOpacityMicromapExecutionModeKHR",
"value" : 6032,
"capabilities" : [ "Shader" ],
"extensions" : [ "SPV_KHR_opacity_micromap" ],
"version" : "None"
},
{
"enumerant" : "AtomicFloat32AddEXT",
"value" : 6033,
@@ -18533,9 +18605,10 @@
"version" : "None"
},
{
"enumerant" : "SplitBarrierINTEL",
"enumerant" : "SplitBarrierEXT",
"aliases" : [ "SplitBarrierINTEL" ],
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
"extensions" : [ "SPV_EXT_split_barrier", "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
@@ -18659,6 +18732,18 @@
"provisional" : true,
"version": "None"
},
{
"enumerant" : "PredicatedIOINTEL",
"value" : 6257,
"extensions" : [ "SPV_INTEL_predicated_io" ],
"version" : "None"
},
{
"enumerant" : "RoundedDivideSqrtINTEL",
"value" : 6265,
"extensions" : [ "SPV_INTEL_rounded_divide_sqrt" ],
"version": "None"
},
{
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
@@ -18962,6 +19047,15 @@
],
"capabilities" : [ "CooperativeMatrixBlockLoadsNV" ],
"version" : "None"
},
{
"enumerant" : "DecodeVectorFunc",
"value" : "0x0004",
"parameters" : [
{ "kind" : "IdRef" }
],
"capabilities" : [ "CooperativeMatrixDecodeVectorNV" ],
"version" : "None"
}
]
},
3rdparty/spirv-headers/include/spirv/unified1/spirv.h
Vendored
+38 -8
View File
@@ -63,6 +63,7 @@ typedef enum SpvSourceLanguage_ {
SpvSourceLanguageSlang = 11,
SpvSourceLanguageZig = 12,
SpvSourceLanguageRust = 13,
SpvSourceLanguagePred = 14,
SpvSourceLanguageMax = 0x7fffffff,
} SpvSourceLanguage;
@@ -209,6 +210,7 @@ typedef enum SpvExecutionMode_ {
SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
SpvExecutionModeMaximallyReconvergesKHR = 6023,
SpvExecutionModeFPFastMathDefault = 6028,
SpvExecutionModeOpacityMicromapIdKHR = 6031,
SpvExecutionModeStreamingInterfaceINTEL = 6154,
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
SpvExecutionModeNamedBarrierCountINTEL = 6417,
@@ -475,6 +477,7 @@ typedef enum SpvLinkageType_ {
SpvLinkageTypeExport = 0,
SpvLinkageTypeImport = 1,
SpvLinkageTypeLinkOnceODR = 2,
SpvLinkageTypeWeakAMD = 3,
SpvLinkageTypeMax = 0x7fffffff,
} SpvLinkageType;
@@ -1206,6 +1209,7 @@ typedef enum SpvCapability_ {
SpvCapabilityDescriptorHeapEXT = 5128,
SpvCapabilityConstantDataKHR = 5146,
SpvCapabilityPoisonFreezeKHR = 5156,
SpvCapabilityWeakLinkageAMD = 5181,
SpvCapabilitySampleMaskOverrideCoverageNV = 5249,
SpvCapabilityGeometryShaderPassthroughNV = 5251,
SpvCapabilityShaderViewportIndexLayerEXT = 5254,
@@ -1270,6 +1274,7 @@ typedef enum SpvCapability_ {
SpvCapabilityDemoteToHelperInvocationEXT = 5379,
SpvCapabilityDisplacementMicromapNV = 5380,
SpvCapabilityRayTracingOpacityMicromapEXT = 5381,
SpvCapabilityRayTracingOpacityMicromapKHR = 5381,
SpvCapabilityShaderInvocationReorderNV = 5383,
SpvCapabilityShaderInvocationReorderEXT = 5388,
SpvCapabilityBindlessTextureNV = 5390,
@@ -1291,6 +1296,7 @@ typedef enum SpvCapability_ {
SpvCapabilityCooperativeVectorTrainingNV = 5435,
SpvCapabilityRayTracingClusterAccelerationStructureNV = 5437,
SpvCapabilityTensorAddressingNV = 5439,
SpvCapabilityCooperativeMatrixDecodeVectorNV = 5447,
SpvCapabilitySubgroupShuffleINTEL = 5568,
SpvCapabilitySubgroupBufferBlockIOINTEL = 5569,
SpvCapabilitySubgroupImageBlockIOINTEL = 5570,
@@ -1364,6 +1370,7 @@ typedef enum SpvCapability_ {
SpvCapabilityGroupNonUniformRotateKHR = 6026,
SpvCapabilityFloatControls2 = 6029,
SpvCapabilityFMAKHR = 6030,
SpvCapabilityRayTracingOpacityMicromapExecutionModeKHR = 6032,
SpvCapabilityAtomicFloat32AddEXT = 6033,
SpvCapabilityAtomicFloat64AddEXT = 6034,
SpvCapabilityLongCompositesINTEL = 6089,
@@ -1372,6 +1379,7 @@ typedef enum SpvCapability_ {
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierEXT = 6141,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityArithmeticFenceEXT = 6144,
SpvCapabilityFPGAClusterAttributesV2ALTERA = 6150,
@@ -1396,6 +1404,8 @@ typedef enum SpvCapability_ {
SpvCapabilityUntypedVariableLengthArrayINTEL = 6243,
SpvCapabilitySpecConditionalINTEL = 6245,
SpvCapabilityFunctionVariantsINTEL = 6246,
SpvCapabilityPredicatedIOINTEL = 6257,
SpvCapabilityRoundedDivideSqrtINTEL = 6265,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityTensorFloat32RoundingINTEL = 6425,
SpvCapabilityMaskedGatherScatterINTEL = 6427,
@@ -1422,6 +1432,7 @@ typedef enum SpvRayFlagsShift_ {
SpvRayFlagsSkipTrianglesKHRShift = 8,
SpvRayFlagsSkipAABBsKHRShift = 9,
SpvRayFlagsForceOpacityMicromap2StateEXTShift = 10,
SpvRayFlagsForceOpacityMicromap2StateKHRShift = 10,
SpvRayFlagsMax = 0x7fffffff,
} SpvRayFlagsShift;
@@ -1439,6 +1450,7 @@ typedef enum SpvRayFlagsMask_ {
SpvRayFlagsSkipTrianglesKHRMask = 0x00000100,
SpvRayFlagsSkipAABBsKHRMask = 0x00000200,
SpvRayFlagsForceOpacityMicromap2StateEXTMask = 0x00000400,
SpvRayFlagsForceOpacityMicromap2StateKHRMask = 0x00000400,
} SpvRayFlagsMask;
typedef enum SpvRayQueryIntersection_ {
@@ -1573,6 +1585,7 @@ typedef enum SpvTensorClampMode_ {
typedef enum SpvTensorAddressingOperandsShift_ {
SpvTensorAddressingOperandsTensorViewShift = 0,
SpvTensorAddressingOperandsDecodeFuncShift = 1,
SpvTensorAddressingOperandsDecodeVectorFuncShift = 2,
SpvTensorAddressingOperandsMax = 0x7fffffff,
} SpvTensorAddressingOperandsShift;
@@ -1580,6 +1593,7 @@ typedef enum SpvTensorAddressingOperandsMask_ {
SpvTensorAddressingOperandsMaskNone = 0,
SpvTensorAddressingOperandsTensorViewMask = 0x00000001,
SpvTensorAddressingOperandsDecodeFuncMask = 0x00000002,
SpvTensorAddressingOperandsDecodeVectorFuncMask = 0x00000004,
} SpvTensorAddressingOperandsMask;
typedef enum SpvTensorOperandsShift_ {
@@ -2599,7 +2613,9 @@ typedef enum SpvOp_ {
SpvOpCompositeConstructContinuedINTEL = 6096,
SpvOpConvertFToBF16INTEL = 6116,
SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveEXT = 6142,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitEXT = 6143,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpArithmeticFenceEXT = 6145,
SpvOpTaskSequenceCreateALTERA = 6163,
@@ -2628,6 +2644,8 @@ typedef enum SpvOp_ {
SpvOpSpecConstantArchitectureINTEL = 6252,
SpvOpSpecConstantCapabilitiesINTEL = 6253,
SpvOpConditionalCopyObjectINTEL = 6254,
SpvOpPredicatedLoadINTEL = 6258,
SpvOpPredicatedStoreINTEL = 6259,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
@@ -3458,8 +3476,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpFixedExpALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpPtrCastToCrossWorkgroupALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpCrossWorkgroupCastToPtrALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpReadPipeBlockingALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpWritePipeBlockingALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpReadPipeBlockingALTERA: *hasResult = false; *hasResultType = false; break;
case SpvOpWritePipeBlockingALTERA: *hasResult = false; *hasResultType = false; break;
case SpvOpFPGARegALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break;
@@ -3483,11 +3501,11 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break;
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case SpvOpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break;
@@ -3510,6 +3528,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpPredicatedLoadINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpPredicatedStoreINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
@@ -3545,6 +3565,7 @@ inline const char* SpvSourceLanguageToString(SpvSourceLanguage value) {
case SpvSourceLanguageSlang: return "Slang";
case SpvSourceLanguageZig: return "Zig";
case SpvSourceLanguageRust: return "Rust";
case SpvSourceLanguagePred: return "Pred";
default: return "Unknown";
}
}
@@ -3686,6 +3707,7 @@ inline const char* SpvExecutionModeToString(SpvExecutionMode value) {
case SpvExecutionModeSchedulerTargetFmaxMhzINTEL: return "SchedulerTargetFmaxMhzINTEL";
case SpvExecutionModeMaximallyReconvergesKHR: return "MaximallyReconvergesKHR";
case SpvExecutionModeFPFastMathDefault: return "FPFastMathDefault";
case SpvExecutionModeOpacityMicromapIdKHR: return "OpacityMicromapIdKHR";
case SpvExecutionModeStreamingInterfaceINTEL: return "StreamingInterfaceINTEL";
case SpvExecutionModeRegisterMapInterfaceINTEL: return "RegisterMapInterfaceINTEL";
case SpvExecutionModeNamedBarrierCountINTEL: return "NamedBarrierCountINTEL";
@@ -3885,6 +3907,7 @@ inline const char* SpvLinkageTypeToString(SpvLinkageType value) {
case SpvLinkageTypeExport: return "Export";
case SpvLinkageTypeImport: return "Import";
case SpvLinkageTypeLinkOnceODR: return "LinkOnceODR";
case SpvLinkageTypeWeakAMD: return "WeakAMD";
default: return "Unknown";
}
}
@@ -4375,6 +4398,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityDescriptorHeapEXT: return "DescriptorHeapEXT";
case SpvCapabilityConstantDataKHR: return "ConstantDataKHR";
case SpvCapabilityPoisonFreezeKHR: return "PoisonFreezeKHR";
case SpvCapabilityWeakLinkageAMD: return "WeakLinkageAMD";
case SpvCapabilitySampleMaskOverrideCoverageNV: return "SampleMaskOverrideCoverageNV";
case SpvCapabilityGeometryShaderPassthroughNV: return "GeometryShaderPassthroughNV";
case SpvCapabilityShaderViewportIndexLayerEXT: return "ShaderViewportIndexLayerEXT";
@@ -4438,6 +4462,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityCooperativeVectorTrainingNV: return "CooperativeVectorTrainingNV";
case SpvCapabilityRayTracingClusterAccelerationStructureNV: return "RayTracingClusterAccelerationStructureNV";
case SpvCapabilityTensorAddressingNV: return "TensorAddressingNV";
case SpvCapabilityCooperativeMatrixDecodeVectorNV: return "CooperativeMatrixDecodeVectorNV";
case SpvCapabilitySubgroupShuffleINTEL: return "SubgroupShuffleINTEL";
case SpvCapabilitySubgroupBufferBlockIOINTEL: return "SubgroupBufferBlockIOINTEL";
case SpvCapabilitySubgroupImageBlockIOINTEL: return "SubgroupImageBlockIOINTEL";
@@ -4491,6 +4516,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityGroupNonUniformRotateKHR: return "GroupNonUniformRotateKHR";
case SpvCapabilityFloatControls2: return "FloatControls2";
case SpvCapabilityFMAKHR: return "FMAKHR";
case SpvCapabilityRayTracingOpacityMicromapExecutionModeKHR: return "RayTracingOpacityMicromapExecutionModeKHR";
case SpvCapabilityAtomicFloat32AddEXT: return "AtomicFloat32AddEXT";
case SpvCapabilityAtomicFloat64AddEXT: return "AtomicFloat64AddEXT";
case SpvCapabilityLongCompositesINTEL: return "LongCompositesINTEL";
@@ -4498,7 +4524,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
case SpvCapabilitySplitBarrierEXT: return "SplitBarrierEXT";
case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case SpvCapabilityFPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA";
case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
@@ -4517,6 +4543,8 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityUntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL";
case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL";
case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL";
case SpvCapabilityPredicatedIOINTEL: return "PredicatedIOINTEL";
case SpvCapabilityRoundedDivideSqrtINTEL: return "RoundedDivideSqrtINTEL";
case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL";
case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
@@ -5551,8 +5579,8 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL";
case SpvOpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL";
case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case SpvOpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT";
case SpvOpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT";
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case SpvOpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA";
case SpvOpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA";
@@ -5575,6 +5603,8 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL";
case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL";
case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL";
case SpvOpPredicatedLoadINTEL: return "OpPredicatedLoadINTEL";
case SpvOpPredicatedStoreINTEL: return "OpPredicatedStoreINTEL";
case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11
Vendored
+38 -8
View File
@@ -59,6 +59,7 @@ enum class SourceLanguage : unsigned {
Slang = 11,
Zig = 12,
Rust = 13,
Pred = 14,
Max = 0x7fffffff,
};
@@ -205,6 +206,7 @@ enum class ExecutionMode : unsigned {
SchedulerTargetFmaxMhzINTEL = 5903,
MaximallyReconvergesKHR = 6023,
FPFastMathDefault = 6028,
OpacityMicromapIdKHR = 6031,
StreamingInterfaceINTEL = 6154,
RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
@@ -471,6 +473,7 @@ enum class LinkageType : unsigned {
Export = 0,
Import = 1,
LinkOnceODR = 2,
WeakAMD = 3,
Max = 0x7fffffff,
};
@@ -1202,6 +1205,7 @@ enum class Capability : unsigned {
DescriptorHeapEXT = 5128,
ConstantDataKHR = 5146,
PoisonFreezeKHR = 5156,
WeakLinkageAMD = 5181,
SampleMaskOverrideCoverageNV = 5249,
GeometryShaderPassthroughNV = 5251,
ShaderViewportIndexLayerEXT = 5254,
@@ -1266,6 +1270,7 @@ enum class Capability : unsigned {
DemoteToHelperInvocationEXT = 5379,
DisplacementMicromapNV = 5380,
RayTracingOpacityMicromapEXT = 5381,
RayTracingOpacityMicromapKHR = 5381,
ShaderInvocationReorderNV = 5383,
ShaderInvocationReorderEXT = 5388,
BindlessTextureNV = 5390,
@@ -1287,6 +1292,7 @@ enum class Capability : unsigned {
CooperativeVectorTrainingNV = 5435,
RayTracingClusterAccelerationStructureNV = 5437,
TensorAddressingNV = 5439,
CooperativeMatrixDecodeVectorNV = 5447,
SubgroupShuffleINTEL = 5568,
SubgroupBufferBlockIOINTEL = 5569,
SubgroupImageBlockIOINTEL = 5570,
@@ -1360,6 +1366,7 @@ enum class Capability : unsigned {
GroupNonUniformRotateKHR = 6026,
FloatControls2 = 6029,
FMAKHR = 6030,
RayTracingOpacityMicromapExecutionModeKHR = 6032,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongCompositesINTEL = 6089,
@@ -1368,6 +1375,7 @@ enum class Capability : unsigned {
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -1392,6 +1400,8 @@ enum class Capability : unsigned {
UntypedVariableLengthArrayINTEL = 6243,
SpecConditionalINTEL = 6245,
FunctionVariantsINTEL = 6246,
PredicatedIOINTEL = 6257,
RoundedDivideSqrtINTEL = 6265,
GroupUniformArithmeticKHR = 6400,
TensorFloat32RoundingINTEL = 6425,
MaskedGatherScatterINTEL = 6427,
@@ -1418,6 +1428,7 @@ enum class RayFlagsShift : unsigned {
SkipTrianglesKHR = 8,
SkipAABBsKHR = 9,
ForceOpacityMicromap2StateEXT = 10,
ForceOpacityMicromap2StateKHR = 10,
Max = 0x7fffffff,
};
@@ -1435,6 +1446,7 @@ enum class RayFlagsMask : unsigned {
SkipTrianglesKHR = 0x00000100,
SkipAABBsKHR = 0x00000200,
ForceOpacityMicromap2StateEXT = 0x00000400,
ForceOpacityMicromap2StateKHR = 0x00000400,
};
enum class RayQueryIntersection : unsigned {
@@ -1569,6 +1581,7 @@ enum class TensorClampMode : unsigned {
enum class TensorAddressingOperandsShift : unsigned {
TensorView = 0,
DecodeFunc = 1,
DecodeVectorFunc = 2,
Max = 0x7fffffff,
};
@@ -1576,6 +1589,7 @@ enum class TensorAddressingOperandsMask : unsigned {
MaskNone = 0,
TensorView = 0x00000001,
DecodeFunc = 0x00000002,
DecodeVectorFunc = 0x00000004,
};
enum class TensorOperandsShift : unsigned {
@@ -2595,7 +2609,9 @@ enum class Op : unsigned {
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
@@ -2624,6 +2640,8 @@ enum class Op : unsigned {
OpSpecConstantArchitectureINTEL = 6252,
OpSpecConstantCapabilitiesINTEL = 6253,
OpConditionalCopyObjectINTEL = 6254,
OpPredicatedLoadINTEL = 6258,
OpPredicatedStoreINTEL = 6259,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
@@ -3454,8 +3472,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpFixedExpALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpPtrCastToCrossWorkgroupALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpCrossWorkgroupCastToPtrALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpReadPipeBlockingALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpWritePipeBlockingALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpReadPipeBlockingALTERA: *hasResult = false; *hasResultType = false; break;
case Op::OpWritePipeBlockingALTERA: *hasResult = false; *hasResultType = false; break;
case Op::OpFPGARegALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break;
@@ -3479,11 +3497,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break;
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case Op::OpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break;
@@ -3506,6 +3524,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpPredicatedLoadINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpPredicatedStoreINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
@@ -3541,6 +3561,7 @@ inline const char* SourceLanguageToString(SourceLanguage value) {
case SourceLanguage::Slang: return "Slang";
case SourceLanguage::Zig: return "Zig";
case SourceLanguage::Rust: return "Rust";
case SourceLanguage::Pred: return "Pred";
default: return "Unknown";
}
}
@@ -3682,6 +3703,7 @@ inline const char* ExecutionModeToString(ExecutionMode value) {
case ExecutionMode::SchedulerTargetFmaxMhzINTEL: return "SchedulerTargetFmaxMhzINTEL";
case ExecutionMode::MaximallyReconvergesKHR: return "MaximallyReconvergesKHR";
case ExecutionMode::FPFastMathDefault: return "FPFastMathDefault";
case ExecutionMode::OpacityMicromapIdKHR: return "OpacityMicromapIdKHR";
case ExecutionMode::StreamingInterfaceINTEL: return "StreamingInterfaceINTEL";
case ExecutionMode::RegisterMapInterfaceINTEL: return "RegisterMapInterfaceINTEL";
case ExecutionMode::NamedBarrierCountINTEL: return "NamedBarrierCountINTEL";
@@ -3881,6 +3903,7 @@ inline const char* LinkageTypeToString(LinkageType value) {
case LinkageType::Export: return "Export";
case LinkageType::Import: return "Import";
case LinkageType::LinkOnceODR: return "LinkOnceODR";
case LinkageType::WeakAMD: return "WeakAMD";
default: return "Unknown";
}
}
@@ -4371,6 +4394,7 @@ inline const char* CapabilityToString(Capability value) {
case Capability::DescriptorHeapEXT: return "DescriptorHeapEXT";
case Capability::ConstantDataKHR: return "ConstantDataKHR";
case Capability::PoisonFreezeKHR: return "PoisonFreezeKHR";
case Capability::WeakLinkageAMD: return "WeakLinkageAMD";
case Capability::SampleMaskOverrideCoverageNV: return "SampleMaskOverrideCoverageNV";
case Capability::GeometryShaderPassthroughNV: return "GeometryShaderPassthroughNV";
case Capability::ShaderViewportIndexLayerEXT: return "ShaderViewportIndexLayerEXT";
@@ -4434,6 +4458,7 @@ inline const char* CapabilityToString(Capability value) {
case Capability::CooperativeVectorTrainingNV: return "CooperativeVectorTrainingNV";
case Capability::RayTracingClusterAccelerationStructureNV: return "RayTracingClusterAccelerationStructureNV";
case Capability::TensorAddressingNV: return "TensorAddressingNV";
case Capability::CooperativeMatrixDecodeVectorNV: return "CooperativeMatrixDecodeVectorNV";
case Capability::SubgroupShuffleINTEL: return "SubgroupShuffleINTEL";
case Capability::SubgroupBufferBlockIOINTEL: return "SubgroupBufferBlockIOINTEL";
case Capability::SubgroupImageBlockIOINTEL: return "SubgroupImageBlockIOINTEL";
@@ -4487,6 +4512,7 @@ inline const char* CapabilityToString(Capability value) {
case Capability::GroupNonUniformRotateKHR: return "GroupNonUniformRotateKHR";
case Capability::FloatControls2: return "FloatControls2";
case Capability::FMAKHR: return "FMAKHR";
case Capability::RayTracingOpacityMicromapExecutionModeKHR: return "RayTracingOpacityMicromapExecutionModeKHR";
case Capability::AtomicFloat32AddEXT: return "AtomicFloat32AddEXT";
case Capability::AtomicFloat64AddEXT: return "AtomicFloat64AddEXT";
case Capability::LongCompositesINTEL: return "LongCompositesINTEL";
@@ -4494,7 +4520,7 @@ inline const char* CapabilityToString(Capability value) {
case Capability::AtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
case Capability::DebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case Capability::BFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
case Capability::SplitBarrierINTEL: return "SplitBarrierINTEL";
case Capability::SplitBarrierEXT: return "SplitBarrierEXT";
case Capability::ArithmeticFenceEXT: return "ArithmeticFenceEXT";
case Capability::FPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA";
case Capability::FPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
@@ -4513,6 +4539,8 @@ inline const char* CapabilityToString(Capability value) {
case Capability::UntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL";
case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL";
case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL";
case Capability::PredicatedIOINTEL: return "PredicatedIOINTEL";
case Capability::RoundedDivideSqrtINTEL: return "RoundedDivideSqrtINTEL";
case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL";
case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
@@ -5547,8 +5575,8 @@ inline const char* OpToString(Op value) {
case Op::OpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL";
case Op::OpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL";
case Op::OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case Op::OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case Op::OpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT";
case Op::OpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT";
case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case Op::OpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA";
case Op::OpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA";
@@ -5571,6 +5599,8 @@ inline const char* OpToString(Op value) {
case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL";
case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL";
case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL";
case Op::OpPredicatedLoadINTEL: return "OpPredicatedLoadINTEL";
case Op::OpPredicatedStoreINTEL: return "OpPredicatedStoreINTEL";
case Op::OpGroupIMulKHR: return "OpGroupIMulKHR";
case Op::OpGroupFMulKHR: return "OpGroupFMulKHR";
case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
3rdparty/spirv-headers/include/spirv/unified1/spirv.json
Vendored
+20 -4
View File
@@ -65,7 +65,8 @@
"WGSL": 10,
"Slang": 11,
"Zig": 12,
"Rust": 13
"Rust": 13,
"Pred": 14
}
},
{
@@ -224,6 +225,7 @@
"SchedulerTargetFmaxMhzINTEL": 5903,
"MaximallyReconvergesKHR": 6023,
"FPFastMathDefault": 6028,
"OpacityMicromapIdKHR": 6031,
"StreamingInterfaceINTEL": 6154,
"RegisterMapInterfaceINTEL": 6160,
"NamedBarrierCountINTEL": 6417,
@@ -484,7 +486,8 @@
{
"Export": 0,
"Import": 1,
"LinkOnceODR": 2
"LinkOnceODR": 2,
"WeakAMD": 3
}
},
{
@@ -1168,6 +1171,7 @@
"DescriptorHeapEXT": 5128,
"ConstantDataKHR": 5146,
"PoisonFreezeKHR": 5156,
"WeakLinkageAMD": 5181,
"SampleMaskOverrideCoverageNV": 5249,
"GeometryShaderPassthroughNV": 5251,
"ShaderViewportIndexLayerEXT": 5254,
@@ -1232,6 +1236,7 @@
"DemoteToHelperInvocationEXT": 5379,
"DisplacementMicromapNV": 5380,
"RayTracingOpacityMicromapEXT": 5381,
"RayTracingOpacityMicromapKHR": 5381,
"ShaderInvocationReorderNV": 5383,
"ShaderInvocationReorderEXT": 5388,
"BindlessTextureNV": 5390,
@@ -1253,6 +1258,7 @@
"CooperativeVectorTrainingNV": 5435,
"RayTracingClusterAccelerationStructureNV": 5437,
"TensorAddressingNV": 5439,
"CooperativeMatrixDecodeVectorNV": 5447,
"SubgroupShuffleINTEL": 5568,
"SubgroupBufferBlockIOINTEL": 5569,
"SubgroupImageBlockIOINTEL": 5570,
@@ -1326,6 +1332,7 @@
"GroupNonUniformRotateKHR": 6026,
"FloatControls2": 6029,
"FMAKHR": 6030,
"RayTracingOpacityMicromapExecutionModeKHR": 6032,
"AtomicFloat32AddEXT": 6033,
"AtomicFloat64AddEXT": 6034,
"LongCompositesINTEL": 6089,
@@ -1334,6 +1341,7 @@
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
"BFloat16ConversionINTEL": 6115,
"SplitBarrierEXT": 6141,
"SplitBarrierINTEL": 6141,
"ArithmeticFenceEXT": 6144,
"FPGAClusterAttributesV2ALTERA": 6150,
@@ -1358,6 +1366,8 @@
"UntypedVariableLengthArrayINTEL": 6243,
"SpecConditionalINTEL": 6245,
"FunctionVariantsINTEL": 6246,
"PredicatedIOINTEL": 6257,
"RoundedDivideSqrtINTEL": 6265,
"GroupUniformArithmeticKHR": 6400,
"TensorFloat32RoundingINTEL": 6425,
"MaskedGatherScatterINTEL": 6427,
@@ -1386,7 +1396,8 @@
"SkipBuiltinPrimitivesNV": 8,
"SkipTrianglesKHR": 8,
"SkipAABBsKHR": 9,
"ForceOpacityMicromap2StateEXT": 10
"ForceOpacityMicromap2StateEXT": 10,
"ForceOpacityMicromap2StateKHR": 10
}
},
{
@@ -1542,7 +1553,8 @@
"Values":
{
"TensorView": 0,
"DecodeFunc": 1
"DecodeFunc": 1,
"DecodeVectorFunc": 2
}
},
{
@@ -2566,7 +2578,9 @@
"OpCompositeConstructContinuedINTEL": 6096,
"OpConvertFToBF16INTEL": 6116,
"OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveEXT": 6142,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitEXT": 6143,
"OpControlBarrierWaitINTEL": 6143,
"OpArithmeticFenceEXT": 6145,
"OpTaskSequenceCreateALTERA": 6163,
@@ -2595,6 +2609,8 @@
"OpSpecConstantArchitectureINTEL": 6252,
"OpSpecConstantCapabilitiesINTEL": 6253,
"OpConditionalCopyObjectINTEL": 6254,
"OpPredicatedLoadINTEL": 6258,
"OpPredicatedStoreINTEL": 6259,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,